This invention relates to input-output (I/O) circuitry for integrated circuits, and more particularly, to high-speed differential input buffers using elevated power supplies.
Input-output (I/O) circuitry is used on integrated circuits as an interface between the circuitry on the integrated circuit and external circuitry. Input-output circuitry typically includes either single-ended or differential input buffers and single-ended or differential output buffers.
Single-ended buffers are used to handle single-ended signals—i.e., signals that are referenced to ground.
Differential I/O buffers are used to handle differential signals. With differential signaling schemes, a pair of signal wires carries the signals between an external component and the integrated circuit. A pair of I/O pads on the integrated circuit is used to route the differential signals to or from associated differential I/O buffers on the integrated circuit.
Differential signals are referenced to each other, rather than a source of ground potential. One of the differential signals in each differential signal pair may be labeled “positive” and the other one of the differential signals in that pair may be labeled “negative.”
The average input voltage of a differential signal is called its “common mode” voltage. Different types of differential signaling schemes impose different constraints on the average signals level of the differential signal pair (i.e., its common mode voltage) and on the maximum difference between the positive and negative signals.
In relatively flexible input-output schemes such as the well-known low-voltage-differential-signaling (LVDS) scheme, the common mode voltage of the differential input signal is allowed to fall anywhere within a fairly large range. While this flexibility is advantageous for system designers, it poses challenges for designers of input-output buffer circuitry.
For example, known high-speed differential input buffers on programmable logic devices have been designed to accommodate a wide range of common-mode voltages by using multiple input buffers arrayed in parallel. The task of handling the differential input signals can be shared between a high-common-mode-voltage input buffer and a low-common-mode-voltage input buffer.
These parallel programmable-logic-device differential input buffers are powered off of the power supply used to power the core logic on the programmable logic device. The voltage associated with this power supply is about 1.5 V.
Although this scheme is generally satisfactory, the delay associated with the input buffer (which is a direct measure of the input buffer's performance) is sometimes greater than desired.
It is therefore an object of the present invention to provide improved differential input buffers for integrated circuits.